apu
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@ -35,6 +35,7 @@ pub struct Apu {
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tnd_table: Vec<f32>,
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frame_counter: u8,
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current_frame: u8,
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mode: u8,
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interrupt_inhibit: u8,
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frame_interrupt: bool,
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@ -65,6 +66,7 @@ impl Apu {
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tnd_table: tnd_table,
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frame_counter: 0,
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current_frame: 0,
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mode: 0,
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interrupt_inhibit: 0,
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frame_interrupt: false,
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@ -100,7 +102,7 @@ impl Apu {
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0x4014 => (),
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0x4015 => self.control(value),
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0x4016 => (),
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0x4017 => self.step_frame_counter(value),
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0x4017 => self.set_frame_counter(value),
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_ => panic!("bad address written: 0x{:X}", address),
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}
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}
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@ -116,7 +118,7 @@ impl Apu {
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// - - - f - - - - - IRQ (if bit 6 is clear)
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// - l - l - l - - l Length counter and sweep
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// e e e e e e e - e Envelope and linear counter
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fn step_frame_counter(&mut self, value: u8) {
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fn set_frame_counter(&mut self, value: u8) {
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// 0 selects 4-step sequence, 1 selects 5-step sequence
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if value & (1<<7) == 0 {
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self.mode = 0;
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@ -132,6 +134,27 @@ impl Apu {
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}
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fn step_frame_counter(&mut self) {
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match self.frame_counter {
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4 => {
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self.square1.clock_envelope();
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self.square2.clock_envelope();
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self.triangle.clock_linear_counter();
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self.noise.clock_envelope();
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if self.current_frame == 1 || self.current_frame == 3 {
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}
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if self.current_frame == 3 {
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self.issue_irq();
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}
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},
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5 => {
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},
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_ => panic!("invalid frame counter value"),
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}
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}
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fn control(&mut self, value: u8) {
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// Writing to this register clears the DMC interrupt flag.
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self.dmc.interrupt = false;
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@ -213,4 +236,8 @@ impl Apu {
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// TODO: If an interrupt flag was set at the same moment of the read, it will read back as 1 but it will not be cleared.
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val
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}
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fn issue_irq(&mut self) {
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}
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}
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@ -39,6 +39,10 @@ impl Noise {
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}
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pub fn clock_envelope(&mut self) {
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}
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pub fn loop_noise(&mut self, value: u8) {
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}
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@ -31,4 +31,8 @@ impl Triangle {
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pub fn counter(&mut self, value: u8) {
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}
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pub fn clock_linear_counter(&mut self) {
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}
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}
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