From c8916baf74d47e6bc538d58e7c8d162e4871600c Mon Sep 17 00:00:00 2001
From: Theron Spiegl <tspiegl@gmail.com>
Date: Wed, 29 Jan 2020 21:22:30 -0600
Subject: [PATCH] mmc3

---
 src/cartridge/mmc3.rs    | 19 ++++++++++++++++---
 src/main.rs              |  8 ++++++++
 src/ppu/cpu_registers.rs |  1 -
 src/ppu/mod.rs           | 31 +++++++++++--------------------
 4 files changed, 35 insertions(+), 24 deletions(-)

diff --git a/src/cartridge/mmc3.rs b/src/cartridge/mmc3.rs
index c975a50..0e10007 100644
--- a/src/cartridge/mmc3.rs
+++ b/src/cartridge/mmc3.rs
@@ -12,6 +12,7 @@ pub struct Mmc3 {
     irq_enable: bool,
     trigger_irq: bool, // signal to send to CPU
     reload_counter: bool,
+    irq_delay: u8,
 
     prg_ram_bank: Vec<u8>, // CPU $6000-$7FFF
     // 0: $8000-$9FFF swappable, $C000-$DFFF fixed to second-last bank
@@ -37,6 +38,7 @@ impl Mmc3 {
             irq_enable: false,
             trigger_irq: false,
             reload_counter: false,
+            irq_delay: 0,
             prg_ram_bank: vec![0; 0x2000],
             prg_rom_bank_mode: false,
             chr_rom_bank_mode: false,
@@ -206,11 +208,22 @@ impl Mapper for Mmc3 {
     }
 
     fn check_irq(&mut self) -> bool {
+        // if self.trigger_irq {
+        //     self.trigger_irq = false;
+        //     true
+        // } else {
+        //     false
+        // }
         if self.trigger_irq {
             self.trigger_irq = false;
-            true
-        } else {
-            false
+            self.irq_delay = 15;
         }
+        if self.irq_delay > 0 {
+            self.irq_delay -= 1;
+            if self.irq_delay == 0 {
+                return true;
+            }
+        }
+        false
     }
 }
diff --git a/src/main.rs b/src/main.rs
index 0fd8f25..d55c311 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -142,4 +142,12 @@ Failed tests from instr_test-v5/rom_singles/:
     CB AXS #n
 7, abs_xy, 'illegal opcode using abs x: 9c'
 
+
+
+
+
+
+1. A12 stuff controls when IRQs 
+2. Don't think the timing stuff is related to the palette and background table issues in SMB3
+
 */
diff --git a/src/ppu/cpu_registers.rs b/src/ppu/cpu_registers.rs
index 27cacf0..5be045a 100644
--- a/src/ppu/cpu_registers.rs
+++ b/src/ppu/cpu_registers.rs
@@ -99,7 +99,6 @@ impl super::Ppu {
 
     // cpu writes to 0x2006, PPUADDR
     pub fn write_address(&mut self, val: u8) {
-        self.mapper.borrow_mut().clock();
         let d = val as u16;
         match self.w { // first write
             0 => {
diff --git a/src/ppu/mod.rs b/src/ppu/mod.rs
index b9af746..2c68713 100644
--- a/src/ppu/mod.rs
+++ b/src/ppu/mod.rs
@@ -88,6 +88,8 @@ pub struct Ppu {
 
     read_buffer:                   u8,   // used with PPUDATA register
     pub recent_bits:               u8,   // Least significant bits previously written into a PPU register
+
+    previous_a12:                  u8,
 }
 
 impl Ppu {
@@ -144,6 +146,7 @@ impl Ppu {
             nmi_delay:                     0,
             read_buffer:                   0,
             recent_bits:                   0,
+            previous_a12:                  0,
         }
     }
 
@@ -243,29 +246,17 @@ impl Ppu {
         }
 
         // deal with mapper MMC3
-        // if self.rendering()
-        // && (1..241).contains(&self.scanline)
-        // && (
-        //     (
-        //         self.line_cycle == 260
-        //         && self.sprite_size == 8
-        //         && self.background_pattern_table_base == 0x0000
-        //         && self.sprite_pattern_table_base == 0x1000
-        //     ) || (
-        //         self.line_cycle == 324
-        //         && self.sprite_size == 8
-        //         && self.background_pattern_table_base == 0x1000
-        //         && self.sprite_pattern_table_base == 0x0000
-        //     ) || (
-        //         self.line_cycle == 260
-        //         && self.sprite_size == 16
-        //         // TODO: figure out exact conditions here
-        //     )
-        // )
-        if self.rendering() && self.line_cycle == 260 && (1..241).contains(&self.scanline)
+        let current_a12 = if self.v & 1 << 12 != 0 { 1 } else { 0 };
+        if rendering
+            && (0..241).contains(&self.scanline)
+            // && (current_a12 == 1 && self.previous_a12 == 0)
+            && current_a12 != self.previous_a12
         {
+            // println!("clocking");
             self.mapper.borrow_mut().clock()
         }
+        // println!("current: {}, previous: {}", current_a12, self.previous_a12);
+        self.previous_a12 = current_a12;
 
         (pixel, end_of_frame)
     }