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this has kirby looking mostly normal. bar still shakes when scrolling vertically and is off by a few pixels normally, but much improved. smb3 is still bad, worse once level starts.

This commit is contained in:
Theron Spiegl 2020-01-25 15:40:52 -06:00
parent 8c6899589d
commit ea752bc4c2
3 changed files with 34 additions and 16 deletions
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14
src/cartridge/mmc3.rs
View File

@ -11,6 +11,7 @@ pub struct Mmc3 {
irq_counter: u8,
irq_enable: bool,
trigger_irq: bool, // signal to send to CPU
reload_counter: bool,
prg_ram_bank: Vec<u8>, // CPU $6000-$7FFF
// 0: $8000-$9FFF swappable, $C000-$DFFF fixed to second-last bank
@ -35,6 +36,7 @@ impl Mmc3 {
irq_counter: 0,
irq_enable: false,
trigger_irq: false,
reload_counter: false,
prg_ram_bank: vec![0; 0x2000],
prg_rom_bank_mode: false,
chr_rom_bank_mode: false,
@ -163,7 +165,7 @@ impl Mapper for Mmc3 {
0x6000..=0x7FFF => self.prg_ram_bank[address % 0x2000] = value, // PRG-RAM
0x8000..=0x9FFF => self.bank_data(value),
0xA000..=0xBFFF => self.prg_ram_protect(),
0xC000..=0xDFFF => self.irq_counter = 0, // Writing any value to this register reloads the MMC3 IRQ counter at the NEXT rising edge of the PPU address, presumably at PPU cycle 260 of the current scanline.
0xC000..=0xDFFF => self.reload_counter = true, // Writing any value to this register reloads the MMC3 IRQ counter at the NEXT rising edge of the PPU address, presumably at PPU cycle 260 of the current scanline.
0xE000..=0xFFFF => self.irq_enable = true,
_ => println!("bad address written to MMC3: 0x{:X}", address),
}
@ -183,8 +185,18 @@ impl Mapper for Mmc3 {
fn save_battery_backed_ram(&self) {}
fn clock(&mut self) {
if self.reload_counter {
self.irq_counter = self.irq_latch;
self.reload_counter = false;
}
// "Should reload and set IRQ every clock when reload is 0."
if self.irq_latch == 0 && self.irq_enable {
self.irq_counter = self.irq_latch;
self.trigger_irq = true;
}
if self.irq_counter == 0 {
self.irq_counter = self.irq_latch;
return;
} else {
self.irq_counter -= 1;
}

1
src/ppu/cpu_registers.rs
View File

@ -99,6 +99,7 @@ impl super::Ppu {
// cpu writes to 0x2006, PPUADDR
pub fn write_address(&mut self, val: u8) {
self.mapper.borrow_mut().clock();
let d = val as u16;
match self.w { // first write
0 => {

35
src/ppu/mod.rs
View File

@ -243,21 +243,26 @@ impl Ppu {
}
// deal with mapper MMC3
if self.rendering() && (
self.line_cycle == 260
&& self.sprite_size == 8
&& self.background_pattern_table_base == 0x0000
&& self.sprite_pattern_table_base == 0x1000
) || (
self.line_cycle == 324
&& self.sprite_size == 8
&& self.background_pattern_table_base == 0x1000
&& self.sprite_pattern_table_base == 0x0000
) || (
self.line_cycle == 260
&& self.sprite_size == 16
// TODO: figure out exact conditions here
)
// if self.rendering()
// && (1..241).contains(&self.scanline)
// && (
// (
// self.line_cycle == 260
// && self.sprite_size == 8
// && self.background_pattern_table_base == 0x0000
// && self.sprite_pattern_table_base == 0x1000
// ) || (
// self.line_cycle == 324
// && self.sprite_size == 8
// && self.background_pattern_table_base == 0x1000
// && self.sprite_pattern_table_base == 0x0000
// ) || (
// self.line_cycle == 260
// && self.sprite_size == 16
// // TODO: figure out exact conditions here
// )
// )
if self.rendering() && self.line_cycle == 260 && (1..241).contains(&self.scanline)
{
self.mapper.borrow_mut().clock()
}