making debug output more readable, notes
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Theron Spiegl
parent
457bad1544
commit
b8a6befb61
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@ -28,21 +28,21 @@ pub enum Mode {
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type AddressingFunction = fn(&mut Cpu) -> usize;
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impl Mode {
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fn get(&self) -> AddressingFunction {
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fn get(&self) -> (AddressingFunction, usize) { // usize is number of bytes the instruction takes, used for debug printing
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match self {
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Mode::ABS => Cpu::absolute,
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Mode::ABX => Cpu::absolute_x,
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Mode::ABY => Cpu::absolute_y,
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Mode::ACC => Cpu::accumulator,
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Mode::IMM => Cpu::immediate,
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Mode::IMP => Cpu::implied,
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Mode::IDX => Cpu::indexed_indirect,
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Mode::IND => Cpu::indirect,
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Mode::INX => Cpu::indirect_indexed,
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Mode::REL => Cpu::relative,
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Mode::ZPG => Cpu::zero_page,
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Mode::ZPX => Cpu::zero_page_x,
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Mode::ZPY => Cpu::zero_page_y,
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Mode::ABS => (Cpu::absolute, 3),
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Mode::ABX => (Cpu::absolute_x, 3),
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Mode::ABY => (Cpu::absolute_y, 3),
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Mode::ACC => (Cpu::accumulator, 1),
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Mode::IMM => (Cpu::immediate, 2),
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Mode::IMP => (Cpu::implied, 1),
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Mode::IDX => (Cpu::indexed_indirect, 2),
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Mode::IND => (Cpu::indirect, 3),
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Mode::INX => (Cpu::indirect_indexed, 2),
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Mode::REL => (Cpu::relative, 2),
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Mode::ZPG => (Cpu::zero_page, 2),
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Mode::ZPX => (Cpu::zero_page_x, 2),
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Mode::ZPY => (Cpu::zero_page_y, 2),
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}
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}
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}
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@ -172,7 +172,8 @@ impl Cpu {
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// get addressing mode
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let mode = self.mode_table[opcode].clone();
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let address = mode.get()(self);
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let (address_func, num_bytes) = mode.get();
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let address = address_func(self);
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// debugging
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let pc = self.PC;
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@ -183,8 +184,14 @@ impl Cpu {
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}
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}
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if self.more > 0 {
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print!("{:04X} {:02X} [{:02x} {:02x}] A:{:02X} X:{:02X} Y:{:02X} P:{:02X} SP:{:02X}",
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pc, self.read(pc), self.read(pc + 1), self.read(pc+2),
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let operands = match num_bytes {
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1 => " ".to_string(),
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2 => format!("{:02X} ", self.read(pc + 1)),
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3 => format!("{:02X} {:02X}", self.read(pc + 1), self.read(pc+2)),
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_ => "error".to_string(),
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};
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print!("{:04X} {:02X} {} {} A:{:02X} X:{:02X} Y:{:02X} P:{:02X} SP:{:02X}",
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pc, self.read(pc), operands, OPCODE_DISPLAY_NAMES[opcode],
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self.A, self.X, self.Y, self.P, self.S,
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);
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let mut zpg = Vec::<u8>::new();
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@ -310,3 +317,39 @@ $4000-$4017 $0018 NES APU and I/O registers
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$4018-$401F $0008 APU and I/O functionality that is normally disabled. See CPU Test Mode.
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$4020-$FFFF $BFE0 Cartridge space: PRG ROM, PRG RAM, and mapper registers (See Note)
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*/
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// For debug output
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const OPCODE_DISPLAY_NAMES: [&str; 256] = [
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"BRK", "ORA", "BAD", "SLO", "NOP", "ORA", "ASL", "SLO",
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"PHP", "ORA", "ASL", "ANC", "NOP", "ORA", "ASL", "SLO",
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"BPL", "ORA", "BAD", "SLO", "NOP", "ORA", "ASL", "SLO",
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"CLC", "ORA", "NOP", "SLO", "NOP", "ORA", "ASL", "SLO",
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"JSR", "AND", "BAD", "RLA", "BIT", "AND", "ROL", "RLA",
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"PLP", "AND", "ROL", "ANC", "BIT", "AND", "ROL", "RLA",
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"BMI", "AND", "BAD", "RLA", "NOP", "AND", "ROL", "RLA",
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"SEC", "AND", "NOP", "RLA", "NOP", "AND", "ROL", "RLA",
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"RTI", "EOR", "BAD", "SRE", "NOP", "EOR", "LSR", "SRE",
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"PHA", "EOR", "LSR", "ALR", "JMP", "EOR", "LSR", "SRE",
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"BVC", "EOR", "BAD", "SRE", "NOP", "EOR", "LSR", "SRE",
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"CLI", "EOR", "NOP", "SRE", "NOP", "EOR", "LSR", "SRE",
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"RTS", "ADC", "BAD", "RRA", "NOP", "ADC", "ROR", "RRA",
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"PLA", "ADC", "ROR", "ARR", "JMP", "ADC", "ROR", "RRA",
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"BVS", "ADC", "BAD", "RRA", "NOP", "ADC", "ROR", "RRA",
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"SEI", "ADC", "NOP", "RRA", "NOP", "ADC", "ROR", "RRA",
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"NOP", "STA", "NOP", "SAX", "STY", "STA", "STX", "SAX",
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"DEY", "NOP", "TXA", "XAA", "STY", "STA", "STX", "SAX",
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"BCC", "STA", "BAD", "AHX", "STY", "STA", "STX", "SAX",
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"TYA", "STA", "TXS", "TAS", "SHY", "STA", "SHX", "AHX",
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"LDY", "LDA", "LDX", "LAX", "LDY", "LDA", "LDX", "LAX",
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"TAY", "LDA", "TAX", "LAX", "LDY", "LDA", "LDX", "LAX",
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"BCS", "LDA", "BAD", "LAX", "LDY", "LDA", "LDX", "LAX",
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"CLV", "LDA", "TSX", "LAS", "LDY", "LDA", "LDX", "LAX",
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"CPY", "CMP", "NOP", "DCP", "CPY", "CMP", "DEC", "DCP",
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"INY", "CMP", "DEX", "AXS", "CPY", "CMP", "DEC", "DCP",
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"BNE", "CMP", "BAD", "DCP", "NOP", "CMP", "DEC", "DCP",
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"CLD", "CMP", "NOP", "DCP", "NOP", "CMP", "DEC", "DCP",
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"CPX", "SBC", "NOP", "ISC", "CPX", "SBC", "INC", "ISC",
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"INX", "SBC", "NOP", "SBC", "CPX", "SBC", "INC", "ISC",
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"BEQ", "SBC", "BAD", "ISC", "NOP", "SBC", "INC", "ISC",
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"SED", "SBC", "NOP", "ISC", "NOP", "SBC", "INC", "ISC",
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];
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@ -152,4 +152,9 @@ WarpZoneObject<-RunEnemyObjectsCore<-EnemiesAndLoopsCore<-VictoryMode/GameEngine
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ScrollLockObject_Warp<-DecodeAreaData<-ProcessAreaData<-
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Is ParseRow0e a clue?
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I think L_UndergroundArea3 is the data for the coin rooms. Need to verify that it's loaded properly.
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It's at 0x2D89 in the ROM, so 0x2D79 without header. Which means it's in PRG ROM, because it's within the first 0x4000,
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in the first PRG chunk/vec given to CPU by cartridge. Because it's NROM, that will be mapped starting at $8000,
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so its position in memory should be 0x8000 + 0x2D79 = 0xAD79.
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*/
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