mmc3
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@ -12,6 +12,7 @@ pub struct Mmc3 {
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irq_enable: bool,
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irq_enable: bool,
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trigger_irq: bool, // signal to send to CPU
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trigger_irq: bool, // signal to send to CPU
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reload_counter: bool,
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reload_counter: bool,
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irq_delay: u8,
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prg_ram_bank: Vec<u8>, // CPU $6000-$7FFF
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prg_ram_bank: Vec<u8>, // CPU $6000-$7FFF
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// 0: $8000-$9FFF swappable, $C000-$DFFF fixed to second-last bank
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// 0: $8000-$9FFF swappable, $C000-$DFFF fixed to second-last bank
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@ -37,6 +38,7 @@ impl Mmc3 {
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irq_enable: false,
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irq_enable: false,
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trigger_irq: false,
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trigger_irq: false,
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reload_counter: false,
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reload_counter: false,
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irq_delay: 0,
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prg_ram_bank: vec![0; 0x2000],
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prg_ram_bank: vec![0; 0x2000],
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prg_rom_bank_mode: false,
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prg_rom_bank_mode: false,
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chr_rom_bank_mode: false,
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chr_rom_bank_mode: false,
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@ -206,11 +208,22 @@ impl Mapper for Mmc3 {
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}
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}
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fn check_irq(&mut self) -> bool {
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fn check_irq(&mut self) -> bool {
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// if self.trigger_irq {
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// self.trigger_irq = false;
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// true
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// } else {
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// false
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// }
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if self.trigger_irq {
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if self.trigger_irq {
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self.trigger_irq = false;
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self.trigger_irq = false;
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true
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self.irq_delay = 15;
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} else {
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false
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}
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}
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if self.irq_delay > 0 {
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self.irq_delay -= 1;
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if self.irq_delay == 0 {
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return true;
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}
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}
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false
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}
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}
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}
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}
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@ -142,4 +142,12 @@ Failed tests from instr_test-v5/rom_singles/:
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CB AXS #n
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CB AXS #n
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7, abs_xy, 'illegal opcode using abs x: 9c'
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7, abs_xy, 'illegal opcode using abs x: 9c'
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1. A12 stuff controls when IRQs
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2. Don't think the timing stuff is related to the palette and background table issues in SMB3
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*/
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*/
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@ -99,7 +99,6 @@ impl super::Ppu {
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// cpu writes to 0x2006, PPUADDR
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// cpu writes to 0x2006, PPUADDR
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pub fn write_address(&mut self, val: u8) {
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pub fn write_address(&mut self, val: u8) {
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self.mapper.borrow_mut().clock();
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let d = val as u16;
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let d = val as u16;
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match self.w { // first write
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match self.w { // first write
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0 => {
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0 => {
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@ -88,6 +88,8 @@ pub struct Ppu {
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read_buffer: u8, // used with PPUDATA register
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read_buffer: u8, // used with PPUDATA register
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pub recent_bits: u8, // Least significant bits previously written into a PPU register
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pub recent_bits: u8, // Least significant bits previously written into a PPU register
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previous_a12: u8,
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}
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}
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impl Ppu {
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impl Ppu {
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@ -144,6 +146,7 @@ impl Ppu {
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nmi_delay: 0,
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nmi_delay: 0,
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read_buffer: 0,
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read_buffer: 0,
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recent_bits: 0,
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recent_bits: 0,
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previous_a12: 0,
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}
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}
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}
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}
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@ -243,29 +246,17 @@ impl Ppu {
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}
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}
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// deal with mapper MMC3
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// deal with mapper MMC3
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// if self.rendering()
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let current_a12 = if self.v & 1 << 12 != 0 { 1 } else { 0 };
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// && (1..241).contains(&self.scanline)
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if rendering
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// && (
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&& (0..241).contains(&self.scanline)
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// (
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// && (current_a12 == 1 && self.previous_a12 == 0)
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// self.line_cycle == 260
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&& current_a12 != self.previous_a12
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// && self.sprite_size == 8
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// && self.background_pattern_table_base == 0x0000
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// && self.sprite_pattern_table_base == 0x1000
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// ) || (
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// self.line_cycle == 324
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// && self.sprite_size == 8
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// && self.background_pattern_table_base == 0x1000
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// && self.sprite_pattern_table_base == 0x0000
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// ) || (
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// self.line_cycle == 260
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// && self.sprite_size == 16
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// // TODO: figure out exact conditions here
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// )
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// )
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if self.rendering() && self.line_cycle == 260 && (1..241).contains(&self.scanline)
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{
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{
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// println!("clocking");
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self.mapper.borrow_mut().clock()
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self.mapper.borrow_mut().clock()
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}
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}
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// println!("current: {}, previous: {}", current_a12, self.previous_a12);
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self.previous_a12 = current_a12;
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(pixel, end_of_frame)
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(pixel, end_of_frame)
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}
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}
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